The whole world is at the dawn of the greatest revolution of the mankind-nanotechnology. The influence of nanotechnology is on all branches of engineering and science.

VLSI Design (a branch of nanotechnology) is experiencing tremendous growth due to advances in technology and scaling in size of devices. As designers have to pack more devices in a VLSI chip, the process of generating layouts is also becoming increasingly complex. CAD tools have to deliver effective solutions for vastly scaled up problems and in the presence of very stringent constraints. A designer must understand the problems associated with the design as well as the workings of CAD tools to arrive at early design closure.

This workshop is designed for introducing the future engineers with digital system design and VLSI implementations.

Todays and future advanced VLSI chips can comfortably include over one billion of transistors in a single piece of silicon with an area of a few square millimeters! Obviously, these transistors are not just there randomly, but each device is carefully designed and positioned to do its job, and to interact with other devices and circuits which might be in the neighborhood or sometimes in the far end of the chip! Despite 6-7 electrically isolated metal layers available on-chip, it's not so hard to imagine what a nightmare is to lay out these billion of devices and to route all the interconnections between them!

This might sound cool and challenging enough, but we haven't even scratched the surface yet! It's just the beginning of the story! Even if you have completed the entire layout correctly, still, who knows that the chip will really work? What about all those tough power and performance specifications which must be met in the presence of serious and increasingly large process variations? How do you know that the real chip will operate as you expect. Did you model everything correctly across all process corners? Did you simulate everything correctly? Did you take into account all noise sources? Did you use a correct circuit topology with sufficient robustness against potential noise and signal timing uncertainties? Did you follow all the manufacturing requirements for product reliability and life time? Is that really a high-yield design, where at least over 90% of the chips will work and can be shipped out to customer? .... OR you are just about to fail A Multi-Million Dollar project?

Kit Content:
Xilinx’s CPLD
JTAG programmer
Power adapter.

Course overview:
Digital System Design issues, Combinational logics and Memories.
Sequential logics: FSM, FSMD, ASM Charts, Micro program control, Concept of data path and control path.
VHDL: Simulation and Synthesis
Programmable Logic Devices: CPLD, FPGA, Introduction to reconfigurable computing, Hardware/software co design.
Lab Sessions: Introducing the CPLD kit, Set of experiments (Including the popular Dice game using CPLD)Various Projects discussion.

Workshop Structure
The workshop will comprise of Expert lectures on various topics on Digital system Design and VLSI Design along with lab session using CAD tools on the CPLD kit.
Both Lectures and Lab session get equal weightage.

Duration
3 days

Fees
We are in the process of loading our prices for all the products. These shall be available soon, for any enquiries please get in touch with us. Thanks for bearing with us.